SVE Instruction List by Dougall Johnson
ADD (vectors, predicated): Add vectors (predicated)
ADD Zdn.H, Pg/M, Zdn.H, Zm.H (SVE (SME
svint16_t svadd[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2)
svuint16_t svadd[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
128-bit SVE
For each 16-bit integer set (3) to (1) + (2).
256-bit SVE
For each 16-bit integer set (3) to (1) + (2).
512-bit SVE
For each 16-bit integer set (3) to (1) + (2).
Larger sizes
1024-bit SVE
For each 16-bit integer set (3) to (1) + (2).
2048-bit SVE
For each 16-bit integer set (3) to (1) + (2).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.