SVE Instruction List by Dougall Johnson
See "ADDQV" in the exploration tools

ADDQV: Unsigned add reduction of quadword vector segments

ADDQV Vd.16B, Pg, Zn.B (SVE2.1 (SME2.1

128-bit SVE

Sum corresponding active 8-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add zero.

256-bit SVE

Sum corresponding active 8-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add zero.

512-bit SVE

Sum corresponding active 8-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add zero.

Larger sizes

1024-bit SVE

Sum corresponding active 8-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add zero.

2048-bit SVE

Sum corresponding active 8-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add zero.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.