SVE Instruction List by Dougall Johnson
ADR: Compute vector address
ADR Zd.D, [Zn.D, Zm.D, UXTW #2] (SVE+NS
128-bit SVE
For each 64-bit integer from (2), extend the corresponding unsigned 32-bit integer from (1), and set (3) to (2) + (1) << 2.
256-bit SVE
For each 64-bit integer from (2), extend the corresponding unsigned 32-bit integer from (1), and set (3) to (2) + (1) << 2.
512-bit SVE
For each 64-bit integer from (2), extend the corresponding unsigned 32-bit integer from (1), and set (3) to (2) + (1) << 2.
Larger sizes
1024-bit SVE
For each 64-bit integer from (2), extend the corresponding unsigned 32-bit integer from (1), and set (3) to (2) + (1) << 2.
2048-bit SVE
For each 64-bit integer from (2), extend the corresponding unsigned 32-bit integer from (1), and set (3) to (2) + (1) << 2.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.