SVE Instruction List by Dougall Johnson
AESD (vectors): AES single round decryption
AESD Zdn.B, Zdn.B, Zm.B (SVE2+AES+NS (SSVE-AES+AES
svuint8_t svaesd[_u8](svuint8_t op1, svuint8_t op2)
128-bit SVE
For each 128-bit block, XOR (1) with the corresponding block from (2), then apply AES inverse ShiftRows and inverse SubBytes, writing the result to (3). This is one round of AES decryption without inverse MixColumns (used for the final round).
256-bit SVE
For each 128-bit block, XOR (1) with the corresponding block from (2), then apply AES inverse ShiftRows and inverse SubBytes, writing the result to (3). This is one round of AES decryption without inverse MixColumns (used for the final round).
512-bit SVE
For each 128-bit block, XOR (1) with the corresponding block from (2), then apply AES inverse ShiftRows and inverse SubBytes, writing the result to (3). This is one round of AES decryption without inverse MixColumns (used for the final round).
Larger sizes
1024-bit SVE
For each 128-bit block, XOR (1) with the corresponding block from (2), then apply AES inverse ShiftRows and inverse SubBytes, writing the result to (3). This is one round of AES decryption without inverse MixColumns (used for the final round).
2048-bit SVE
For each 128-bit block, XOR (1) with the corresponding block from (2), then apply AES inverse ShiftRows and inverse SubBytes, writing the result to (3). This is one round of AES decryption without inverse MixColumns (used for the final round).
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.