SVE Instruction List by Dougall Johnson
AESIMC: AES inverse mix columns
AESIMC Zdn.B, Zdn.B (SVE2+AES+NS (SSVE-AES+AES
svuint8_t svaesimc[_u8](svuint8_t op)
128-bit SVE
For each 128-bit block of (1), apply AES inverse MixColumns and write the result to (2). Typically follows AESD to complete a non-final AES decryption round.
256-bit SVE
For each 128-bit block of (1), apply AES inverse MixColumns and write the result to (2). Typically follows AESD to complete a non-final AES decryption round.
512-bit SVE
For each 128-bit block of (1), apply AES inverse MixColumns and write the result to (2). Typically follows AESD to complete a non-final AES decryption round.
Larger sizes
1024-bit SVE
For each 128-bit block of (1), apply AES inverse MixColumns and write the result to (2). Typically follows AESD to complete a non-final AES decryption round.
2048-bit SVE
For each 128-bit block of (1), apply AES inverse MixColumns and write the result to (2). Typically follows AESD to complete a non-final AES decryption round.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.