SVE Instruction List by Dougall Johnson
ASR (immediate, predicated): Arithmetic shift right by immediate (predicated)
ASR Zdn.H, Pg/M, Zdn.H, #const (SVE (SME
svint16_t svasr[_n_s16]_m(svbool_t pg, svint16_t op1, uint16_t op2)
svint16_t svasr_wide[_n_s16]_m(svbool_t pg, svint16_t op1, uint64_t op2)
128-bit SVE
For each 16-bit signed integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 16.
256-bit SVE
For each 16-bit signed integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 16.
512-bit SVE
For each 16-bit signed integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 16.
Larger sizes
1024-bit SVE
For each 16-bit signed integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 16.
2048-bit SVE
For each 16-bit signed integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 16.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.