SVE Instruction List by Dougall Johnson
ASR (wide elements, predicated): Arithmetic shift right by 64-bit wide elements (predicated)
ASR Zdn.H, Pg/M, Zdn.H, Zm.D (SVE (SME
svint16_t svasr_wide[_s16]_m(svbool_t pg, svint16_t op1, svuint64_t op2)
128-bit SVE
For each 16-bit signed integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 15 or less than 0, every bit of the result is set to the sign bit of (2).
256-bit SVE
For each 16-bit signed integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 15 or less than 0, every bit of the result is set to the sign bit of (2).
512-bit SVE
For each 16-bit signed integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 15 or less than 0, every bit of the result is set to the sign bit of (2).
Larger sizes
1024-bit SVE
For each 16-bit signed integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 15 or less than 0, every bit of the result is set to the sign bit of (2).
2048-bit SVE
For each 16-bit signed integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 15 or less than 0, every bit of the result is set to the sign bit of (2).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.