See "ASR (vectors)" in the exploration tools

ASR (vectors): Arithmetic shift right by vector (predicated)

ASR Zdn.D, Pg/M, Zdn.D, Zm.D (SVE (SME

svint64_t svasr[_s64]_m(svbool_t pg, svint64_t op1, svuint64_t op2)

128-bit SVE

For each 64-bit signed integer set (3) to (1) >> (2). If (2) is greater than 63 or less than 0, every bit of the result is set to the sign bit of (1).

256-bit SVE

For each 64-bit signed integer set (3) to (1) >> (2). If (2) is greater than 63 or less than 0, every bit of the result is set to the sign bit of (1).

512-bit SVE

For each 64-bit signed integer set (3) to (1) >> (2). If (2) is greater than 63 or less than 0, every bit of the result is set to the sign bit of (1).

Larger sizes

1024-bit SVE

For each 64-bit signed integer set (3) to (1) >> (2). If (2) is greater than 63 or less than 0, every bit of the result is set to the sign bit of (1).

2048-bit SVE

For each 64-bit signed integer set (3) to (1) >> (2). If (2) is greater than 63 or less than 0, every bit of the result is set to the sign bit of (1).

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.