SVE Instruction List by Dougall Johnson
ASR (vectors): Arithmetic shift right by vector (predicated)
ASR Zdn.B, Pg/M, Zdn.B, Zm.B (SVE (SME
svint8_t svasr[_s8]_m(svbool_t pg, svint8_t op1, svuint8_t op2)
128-bit SVE
For each 8-bit signed integer set (3) to (1) >> (2). If (2) is greater than 7 or less than 0, every bit of the result is set to the sign bit of (1).
256-bit SVE
For each 8-bit signed integer set (3) to (1) >> (2). If (2) is greater than 7 or less than 0, every bit of the result is set to the sign bit of (1).
512-bit SVE
For each 8-bit signed integer set (3) to (1) >> (2). If (2) is greater than 7 or less than 0, every bit of the result is set to the sign bit of (1).
Larger sizes
1024-bit SVE
For each 8-bit signed integer set (3) to (1) >> (2). If (2) is greater than 7 or less than 0, every bit of the result is set to the sign bit of (1).
2048-bit SVE
For each 8-bit signed integer set (3) to (1) >> (2). If (2) is greater than 7 or less than 0, every bit of the result is set to the sign bit of (1).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.