SVE Instruction List by Dougall Johnson
# ASRD: Arithmetic shift right for divide by immediate (predicated)

ASRD Zdn.H, Pg/M, Zdn.H, #const (SVE (SME

svint16_t svasrd[_n_s16]_m(svbool_t pg, svint16_t op1, uint64_t imm2)

## 128-bit SVE

For each 16-bit signed integer set (2) to (1) >> const, if (1) is non-negative, or ( (1) + ( 1 << ( const − 1 ) ) >> const, if (1) is negative. This is the same as a regular shift, but rounding the result towards zero. The shift amount is limited to 1 ≤ const ≤ 16.

## 256-bit SVE

For each 16-bit signed integer set (2) to (1) >> const, if (1) is non-negative, or ( (1) + ( 1 << ( const − 1 ) ) >> const, if (1) is negative. This is the same as a regular shift, but rounding the result towards zero. The shift amount is limited to 1 ≤ const ≤ 16.

## 512-bit SVE

For each 16-bit signed integer set (2) to (1) >> const, if (1) is non-negative, or ( (1) + ( 1 << ( const − 1 ) ) >> const, if (1) is negative. This is the same as a regular shift, but rounding the result towards zero. The shift amount is limited to 1 ≤ const ≤ 16.

## Larger sizes

## 1024-bit SVE

For each 16-bit signed integer set (2) to (1) >> const, if (1) is non-negative, or ( (1) + ( 1 << ( const − 1 ) ) >> const, if (1) is negative. This is the same as a regular shift, but rounding the result towards zero. The shift amount is limited to 1 ≤ const ≤ 16.

## 2048-bit SVE

For each 16-bit signed integer set (2) to (1) >> const, if (1) is non-negative, or ( (1) + ( 1 << ( const − 1 ) ) >> const, if (1) is negative. This is the same as a regular shift, but rounding the result towards zero. The shift amount is limited to 1 ≤ const ≤ 16.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.