ASRR: Reversed arithmetic shift right by vector (predicated)

ASRR Zdn.S, Pg/M, Zdn.S, Zm.S (SVE (SME

128-bit SVE

For each 32-bit signed integer set (3) to (2) >> (1). If (1) is greater than 31 or less than 0, every bit of the result is set to the sign bit of (2).

256-bit SVE

For each 32-bit signed integer set (3) to (2) >> (1). If (1) is greater than 31 or less than 0, every bit of the result is set to the sign bit of (2).

512-bit SVE

For each 32-bit signed integer set (3) to (2) >> (1). If (1) is greater than 31 or less than 0, every bit of the result is set to the sign bit of (2).

Larger sizes

1024-bit SVE

For each 32-bit signed integer set (3) to (2) >> (1). If (1) is greater than 31 or less than 0, every bit of the result is set to the sign bit of (2).

2048-bit SVE

For each 32-bit signed integer set (3) to (2) >> (1). If (1) is greater than 31 or less than 0, every bit of the result is set to the sign bit of (2).

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.