COMPACT: Shuffle active elements of vector to the right and fill with zero

COMPACT Zd.D, Pg, Zn.D (SVE+NS

svfloat64_t svcompact[_f64](svbool_t pg, svfloat64_t op)

svint64_t svcompact[_s64](svbool_t pg, svint64_t op)

svuint64_t svcompact[_u64](svbool_t pg, svuint64_t op)

128-bit SVE

Select the 64-bit lanes from (1) where the corresponding predicate bit in (2) is set, and pack them into low lanes of (3), preserving their order, zeroing any high lanes.

256-bit SVE

Select the 64-bit lanes from (1) where the corresponding predicate bit in (2) is set, and pack them into low lanes of (3), preserving their order, zeroing any high lanes.

512-bit SVE

Select the 64-bit lanes from (1) where the corresponding predicate bit in (2) is set, and pack them into low lanes of (3), preserving their order, zeroing any high lanes.

Larger sizes

1024-bit SVE

Select the 64-bit lanes from (1) where the corresponding predicate bit in (2) is set, and pack them into low lanes of (3), preserving their order, zeroing any high lanes.

2048-bit SVE

Select the 64-bit lanes from (1) where the corresponding predicate bit in (2) is set, and pack them into low lanes of (3), preserving their order, zeroing any high lanes.

Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.