FADDA: Floating-point add strictly-ordered reduction, accumulating in scalar

FADDA Ddn, Pg, Ddn, Zm.D (SVE+NS

float64_t svadda[_f64](svbool_t pg, float64_t initial, svfloat64_t op)

128-bit SVE

Add active 64-bit float elements from (2) to a scalar accumulator (1), in order, from lower to upper, storing the result in (3). Inactive elements are skipped.

256-bit SVE

Add active 64-bit float elements from (2) to a scalar accumulator (1), in order, from lower to upper, storing the result in (3). Inactive elements are skipped.

512-bit SVE

Add active 64-bit float elements from (2) to a scalar accumulator (1), in order, from lower to upper, storing the result in (3). Inactive elements are skipped.

Larger sizes

1024-bit SVE

Add active 64-bit float elements from (2) to a scalar accumulator (1), in order, from lower to upper, storing the result in (3). Inactive elements are skipped.

2048-bit SVE

Add active 64-bit float elements from (2) to a scalar accumulator (1), in order, from lower to upper, storing the result in (3). Inactive elements are skipped.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.