SVE Instruction List by Dougall Johnson
FADDQV: Floating-point add recursive reduction of quadword vector segments
FADDQV Vd.2D, Pg, Zn.D (SVE2.1 (SME2.1
128-bit SVE
Sum corresponding active 64-bit float elements from each 128-bit segment of (1), using a tree reduction, storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add +0.0.
256-bit SVE
Sum corresponding active 64-bit float elements from each 128-bit segment of (1), using a tree reduction, storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add +0.0.
512-bit SVE
Sum corresponding active 64-bit float elements from each 128-bit segment of (1), using a tree reduction, storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add +0.0.
Larger sizes
1024-bit SVE
Sum corresponding active 64-bit float elements from each 128-bit segment of (1), using a tree reduction, storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add +0.0.
2048-bit SVE
Sum corresponding active 64-bit float elements from each 128-bit segment of (1), using a tree reduction, storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, instead add +0.0.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.