SVE Instruction List by Dougall Johnson
FADDV: Floating-point add recursive reduction to scalar
FADDV Hd, Pg, Zn.H (SVE (SME
float16_t svaddv[_f16](svbool_t pg, svfloat16_t op)
128-bit SVE
Sum active 16-bit float elements from (1), using a tree reduction, storing the result in (2). Inactive elements are interpreted as +0.0.
256-bit SVE
Sum active 16-bit float elements from (1), using a tree reduction, storing the result in (2). Inactive elements are interpreted as +0.0.
512-bit SVE
Sum active 16-bit float elements from (1), using a tree reduction, storing the result in (2). Inactive elements are interpreted as +0.0.
Larger sizes
1024-bit SVE
Sum active 16-bit float elements from (1), using a tree reduction, storing the result in (2). Inactive elements are interpreted as +0.0.
2048-bit SVE
Sum active 16-bit float elements from (1), using a tree reduction, storing the result in (2). Inactive elements are interpreted as +0.0.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.