SVE Instruction List by Dougall Johnson
FCADD: Floating-point complex add with 270° rotate (predicated)
FCADD Zdn.H, Pg/M, Zdn.H, Zm.H, #270 (SVE (SME
svfloat16_t svcadd[_f16]_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, 270)
128-bit SVE
For each pair of 16-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 270° ).
256-bit SVE
For each pair of 16-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 270° ).
512-bit SVE
For each pair of 16-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 270° ).
Larger sizes
1024-bit SVE
For each pair of 16-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 270° ).
2048-bit SVE
For each pair of 16-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 270° ).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.