SVE Instruction List by Dougall Johnson
FCADD: Floating-point complex add with 90° rotate (predicated)
FCADD Zdn.D, Pg/M, Zdn.D, Zm.D, #90 (SVE (SME
svfloat64_t svcadd[_f64]_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, 90)
128-bit SVE
For each pair of 64-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 90° ).
256-bit SVE
For each pair of 64-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 90° ).
512-bit SVE
For each pair of 64-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 90° ).
Larger sizes
1024-bit SVE
For each pair of 64-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 90° ).
2048-bit SVE
For each pair of 64-bit floats, considered as the real and imaginary components of a complex number, set (3) to (2) + ( (1) rotated by 90° ).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.