SVE Instruction List by Dougall Johnson
FMLA (vectors): Floating-point fused multiply-add vectors (predicated), writing addend [Zda = Zda + Zn * Zm]
FMLA Zda.D, Pg/M, Zn.D, Zm.D (SVE (SME
svfloat64_t svmla[_f64]_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
128-bit SVE
For each 64-bit float set (4) to (1) + (2) * (3).
256-bit SVE
For each 64-bit float set (4) to (1) + (2) * (3).
512-bit SVE
For each 64-bit float set (4) to (1) + (2) * (3).
Larger sizes
1024-bit SVE
For each 64-bit float set (4) to (1) + (2) * (3).
2048-bit SVE
For each 64-bit float set (4) to (1) + (2) * (3).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.