SVE Instruction List by Dougall Johnson
FMLALB (indexed, FP8 to FP16): 8-bit floating-point multiply-add by indexed element to half-precision (bottom)
FMLALB Zda.H, Zn.B, Zm.B[imm] (SVE2+FP8FMA+NS (SSVE-FP8FMA
128-bit SVE
Multiply each even 8-bit float from (2), with the 8-bit float specified by imm from (1), then add this to the 16-bit float from (3), and set (4) to the result. The FP8 format for each 8-bit source operand is selected independently by FPMR.
256-bit SVE
Multiply each even 8-bit float from (2), with the 8-bit float specified by imm from (1), then add this to the 16-bit float from (3), and set (4) to the result. The FP8 format for each 8-bit source operand is selected independently by FPMR.
512-bit SVE
Multiply each even 8-bit float from (2), with the 8-bit float specified by imm from (1), then add this to the 16-bit float from (3), and set (4) to the result. The FP8 format for each 8-bit source operand is selected independently by FPMR.
Larger sizes
1024-bit SVE
Multiply each even 8-bit float from (2), with the 8-bit float specified by imm from (1), then add this to the 16-bit float from (3), and set (4) to the result. The FP8 format for each 8-bit source operand is selected independently by FPMR.
2048-bit SVE
Multiply each even 8-bit float from (2), with the 8-bit float specified by imm from (1), then add this to the 16-bit float from (3), and set (4) to the result. The FP8 format for each 8-bit source operand is selected independently by FPMR.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.