SVE Instruction List by Dougall Johnson
FMLS (indexed): Floating-point fused multiply-subtract by indexed elements (Zda = Zda + -Zn * Zm[indexed])
FMLS Zda.D, Zn.D, Zm.D[imm] (SVE (SME
svfloat64_t svmls_lane[_f64](svfloat64_t op1, svfloat64_t op2, svfloat64_t op3, uint64_t imm_index)
128-bit SVE
Within each 128-bit segment, for each 64-bit float, set (4) to the element from (1) specified by imm, multiplied by (2), minus (3).
256-bit SVE
Within each 128-bit segment, for each 64-bit float, set (4) to the element from (1) specified by imm, multiplied by (2), minus (3).
512-bit SVE
Within each 128-bit segment, for each 64-bit float, set (4) to the element from (1) specified by imm, multiplied by (2), minus (3).
Larger sizes
1024-bit SVE
Within each 128-bit segment, for each 64-bit float, set (4) to the element from (1) specified by imm, multiplied by (2), minus (3).
2048-bit SVE
Within each 128-bit segment, for each 64-bit float, set (4) to the element from (1) specified by imm, multiplied by (2), minus (3).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.