SVE Instruction List by Dougall Johnson
FNMAD: Floating-point negated fused multiply-add vectors (predicated), writing multiplicand [Zdn = -Za + -Zdn * Zm]
FNMAD Zdn.H, Pg/M, Zm.H, Za.H (SVE (SME
svfloat16_t svnmad[_f16]_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
128-bit SVE
For each 16-bit float set (4) to −(3) + −(1) * (2).
256-bit SVE
For each 16-bit float set (4) to −(3) + −(1) * (2).
512-bit SVE
For each 16-bit float set (4) to −(3) + −(1) * (2).
Larger sizes
1024-bit SVE
For each 16-bit float set (4) to −(3) + −(1) * (2).
2048-bit SVE
For each 16-bit float set (4) to −(3) + −(1) * (2).
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.