SVE Instruction List by Dougall Johnson
See "FNMAD" in the exploration tools

FNMAD: Floating-point negated fused multiply-add vectors (predicated), writing multiplicand [Zdn = -Za + -Zdn * Zm]

FNMAD Zdn.D, Pg/M, Zm.D, Za.D (SVE (SME
svfloat64_t svnmad[_f64]_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)

128-bit SVE

For each 64-bit float set (4) to −(3) + −(1) * (2).

256-bit SVE

For each 64-bit float set (4) to −(3) + −(1) * (2).

512-bit SVE

For each 64-bit float set (4) to −(3) + −(1) * (2).
Larger sizes

1024-bit SVE

For each 64-bit float set (4) to −(3) + −(1) * (2).

2048-bit SVE

For each 64-bit float set (4) to −(3) + −(1) * (2).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.