SVE Instruction List by Dougall Johnson
FRINTX: Floating-point round to integral value (predicated)
FRINTX Zd.D, Pg/M, Zn.D (SVE (SME
svfloat64_t svrintx[_f64]_m(svfloat64_t inactive, svbool_t pg, svfloat64_t op)
128-bit SVE
For each 64-bit float round (1) to an integral floating-point value, raising the floating-point inexact exception if rounding occurs, and set (2) to the result. The current rounding mode selected by FPCR is used.
256-bit SVE
For each 64-bit float round (1) to an integral floating-point value, raising the floating-point inexact exception if rounding occurs, and set (2) to the result. The current rounding mode selected by FPCR is used.
512-bit SVE
For each 64-bit float round (1) to an integral floating-point value, raising the floating-point inexact exception if rounding occurs, and set (2) to the result. The current rounding mode selected by FPCR is used.
Larger sizes
1024-bit SVE
For each 64-bit float round (1) to an integral floating-point value, raising the floating-point inexact exception if rounding occurs, and set (2) to the result. The current rounding mode selected by FPCR is used.
2048-bit SVE
For each 64-bit float round (1) to an integral floating-point value, raising the floating-point inexact exception if rounding occurs, and set (2) to the result. The current rounding mode selected by FPCR is used.
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.