SVE Instruction List by Dougall Johnson
FSCALE: Floating-point adjust exponent by vector (predicated)
FSCALE Zdn.D, Pg/M, Zdn.D, Zm.D (SVE (SME
svfloat64_t svscale[_f64]_m(svbool_t pg, svfloat64_t op1, svint64_t op2)
128-bit SVE
For each 64-bit float from (1) and 64-bit signed integer from (2), set (3) to (1) * 2.0(2) as a 64-bit float.
256-bit SVE
For each 64-bit float from (1) and 64-bit signed integer from (2), set (3) to (1) * 2.0(2) as a 64-bit float.
512-bit SVE
For each 64-bit float from (1) and 64-bit signed integer from (2), set (3) to (1) * 2.0(2) as a 64-bit float.
Larger sizes
1024-bit SVE
For each 64-bit float from (1) and 64-bit signed integer from (2), set (3) to (1) * 2.0(2) as a 64-bit float.
2048-bit SVE
For each 64-bit float from (1) and 64-bit signed integer from (2), set (3) to (1) * 2.0(2) as a 64-bit float.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.