SVE Instruction List by Dougall Johnson
INSR (scalar): Insert general-purpose register in shifted vector
INSR Zdn.H, Wm (SVE (SME
svbfloat16_t svinsr[_n_bf16](svbfloat16_t op1, bfloat16_t op2)
svfloat16_t svinsr[_n_f16](svfloat16_t op1, float16_t op2)
svint16_t svinsr[_n_s16](svint16_t op1, int16_t op2)
svuint16_t svinsr[_n_u16](svuint16_t op1, uint16_t op2)
128-bit SVE
Shift the 16-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
256-bit SVE
Shift the 16-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
512-bit SVE
Shift the 16-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
Larger sizes
1024-bit SVE
Shift the 16-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
2048-bit SVE
Shift the 16-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.