SVE Instruction List by Dougall Johnson
INSR (scalar): Insert general-purpose register in shifted vector
INSR Zdn.B, Wm (SVE (SME
svint8_t svinsr[_n_s8](svint8_t op1, int8_t op2)
svuint8_t svinsr[_n_u8](svuint8_t op1, uint8_t op2)
128-bit SVE
Shift the 8-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
256-bit SVE
Shift the 8-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
512-bit SVE
Shift the 8-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
Larger sizes
1024-bit SVE
Shift the 8-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
2048-bit SVE
Shift the 8-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.