SVE Instruction List by Dougall Johnson
INSR (SIMD&FP scalar): Insert SIMD&FP scalar register in shifted vector
INSR Zdn.D, Dm (SVE (SME
svfloat64_t svinsr[_n_f64](svfloat64_t op1, float64_t op2)
svint64_t svinsr[_n_s64](svint64_t op1, int64_t op2)
svuint64_t svinsr[_n_u64](svuint64_t op1, uint64_t op2)
128-bit SVE
Shift the 64-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
256-bit SVE
Shift the 64-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
512-bit SVE
Shift the 64-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
Larger sizes
1024-bit SVE
Shift the 64-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
2048-bit SVE
Shift the 64-bit lanes from (1) left by one element, inserting (2) into lane 0, and setting (3) to the result.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.