LD1B (scalar plus scalar, consecutive registers): Contiguous load of bytes to multiple consecutive vectors (scalar index)

LD1B { Zt1.B, Zt2.B }, PNg/Z, [Xn, Xm] (SVE2.1 (SME2+S

Load 8-bit values from the memory operand (1) into the 8-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.

Load 8-bit values from the memory operand (1) into the 8-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.

Load 8-bit values from the memory operand (1) into the 8-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.