LD1D (scalar plus immediate, consecutive registers): Contiguous load of doublewords to multiple consecutive vectors (immediate index)

LD1D { Zt1.D, Zt2.D }, PNg/Z, [Xn{, #imm, MUL VL}] (SVE2.1 (SME2+S

Load 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.

Load 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.

Load 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.