SVE Instruction List by Dougall Johnson
LD1D (scalar plus scalar, consecutive registers): Contiguous load of doublewords to multiple consecutive vectors (scalar index)
LD1D { Zt1.D, Zt2.D }, PNg/Z, [Xn, Xm, LSL #3] (SVE2.1 (SME2+S
128-bit SVE
Load 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.
256-bit SVE
Load 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.
512-bit SVE
Load 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.
Larger sizes
1024-bit SVE
Load 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.
2048-bit SVE
Load 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). After decoding the predicate from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by two.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.