SVE Instruction List by Dougall Johnson
LD1D (scalar plus scalar, single register): Contiguous load unsigned doublewords to vector (scalar index)
LD1D { Zt.Q }, Pg/Z, [Xn, Xm, LSL #3] (SVE2.1+NS
128-bit SVE
Load 64-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
256-bit SVE
Load 64-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
512-bit SVE
Load 64-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
Larger sizes
1024-bit SVE
Load 64-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
2048-bit SVE
Load 64-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.