SVE Instruction List by Dougall Johnson
# LD1D (scalar plus vector): Gather load doublewords to vector (vector index)

LD1D { Zt.D }, Pg/Z, [Xn, Zm.D, LSL #3] (SVE+NS

svfloat64_t svld1_gather_[s64]index[_f64](svbool_t pg, const float64_t *base, svint64_t indices)

svint64_t svld1_gather_[s64]index[_s64](svbool_t pg, const int64_t *base, svint64_t indices)

svuint64_t svld1_gather_[s64]index[_u64](svbool_t pg, const uint64_t *base, svint64_t indices)

svfloat64_t svld1_gather_[u64]index[_f64](svbool_t pg, const float64_t *base, svuint64_t indices)

svint64_t svld1_gather_[u64]index[_s64](svbool_t pg, const int64_t *base, svuint64_t indices)

svuint64_t svld1_gather_[u64]index[_u64](svbool_t pg, const uint64_t *base, svuint64_t indices)

## 128-bit SVE

Gather (load) 64-bit values into (3), from a base address (Xn/base), plus each corresponding 64-bit index from (2) multiplied by 8. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

## 256-bit SVE

Gather (load) 64-bit values into (3), from a base address (Xn/base), plus each corresponding 64-bit index from (2) multiplied by 8. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

## 512-bit SVE

Gather (load) 64-bit values into (3), from a base address (Xn/base), plus each corresponding 64-bit index from (2) multiplied by 8. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

## Larger sizes

## 1024-bit SVE

Gather (load) 64-bit values into (3), from a base address (Xn/base), plus each corresponding 64-bit index from (2) multiplied by 8. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

## 2048-bit SVE

Gather (load) 64-bit values into (3), from a base address (Xn/base), plus each corresponding 64-bit index from (2) multiplied by 8. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.