SVE Instruction List by Dougall Johnson
LD1H (scalar plus immediate, single register): Contiguous load unsigned halfwords to vector (immediate index)
LD1H { Zt.S }, Pg/Z, [Xn{, #imm, MUL VL}] (SVE (SME
svint32_t svld1uh_vnum_s32(svbool_t pg, const uint16_t *base, int64_t vnum)
svuint32_t svld1uh_vnum_u32(svbool_t pg, const uint16_t *base, int64_t vnum)
128-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
256-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
512-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
Larger sizes
1024-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
2048-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.