SVE Instruction List by Dougall Johnson
LD1H (scalar plus scalar, single register): Contiguous load unsigned halfwords to vector (scalar index)
LD1H { Zt.D }, Pg/Z, [Xn, Xm, LSL #1] (SVE (SME
svint64_t svld1uh_s64(svbool_t pg, const uint16_t *base)
svuint64_t svld1uh_u64(svbool_t pg, const uint16_t *base)
128-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
256-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
512-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
Larger sizes
1024-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
2048-bit SVE
Load 16-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.