SVE Instruction List by Dougall Johnson
LD1Q: Gather load quadwords
LD1Q { Zt.Q }, Pg/Z, [Zn.D{, Xm}] (SVE2.1+NS
128-bit SVE
Gather (load) 128-bit values into (3), from an optional base address (Xn/XZR), plus each corresponding even 64-bit offset from (2). If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
256-bit SVE
Gather (load) 128-bit values into (3), from an optional base address (Xn/XZR), plus each corresponding even 64-bit offset from (2). If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
512-bit SVE
Gather (load) 128-bit values into (3), from an optional base address (Xn/XZR), plus each corresponding even 64-bit offset from (2). If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
Larger sizes
1024-bit SVE
Gather (load) 128-bit values into (3), from an optional base address (Xn/XZR), plus each corresponding even 64-bit offset from (2). If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
2048-bit SVE
Gather (load) 128-bit values into (3), from an optional base address (Xn/XZR), plus each corresponding even 64-bit offset from (2). If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.