SVE Instruction List by Dougall Johnson
LD1RH: Load and broadcast unsigned halfword to vector
LD1RH { Zt.H }, Pg/Z, [Xn, #imm] (SVE (SME
128-bit SVE
Load a single 16-bit value from the memory operand (1), and broadcast it to all 16-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
256-bit SVE
Load a single 16-bit value from the memory operand (1), and broadcast it to all 16-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
512-bit SVE
Load a single 16-bit value from the memory operand (1), and broadcast it to all 16-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
Larger sizes
1024-bit SVE
Load a single 16-bit value from the memory operand (1), and broadcast it to all 16-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
2048-bit SVE
Load a single 16-bit value from the memory operand (1), and broadcast it to all 16-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.