SVE Instruction List by Dougall Johnson
LD1RSH: Load and broadcast signed halfword to vector
LD1RSH { Zt.S }, Pg/Z, [Xn, #imm] (SVE (SME
128-bit SVE
Load a single 16-bit value from the memory operand (1), sign extend it, and broadcast it to all 32-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
256-bit SVE
Load a single 16-bit value from the memory operand (1), sign extend it, and broadcast it to all 32-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
512-bit SVE
Load a single 16-bit value from the memory operand (1), sign extend it, and broadcast it to all 32-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
Larger sizes
1024-bit SVE
Load a single 16-bit value from the memory operand (1), sign extend it, and broadcast it to all 32-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
2048-bit SVE
Load a single 16-bit value from the memory operand (1), sign extend it, and broadcast it to all 32-bit elements of (2). If all predicate bits corresponding to elements in (2) are zero, the load is skipped, and cannot cause a fault.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.