SVE Instruction List by Dougall Johnson
See "LD1SH (scalar plus scalar)" in the exploration tools

LD1SH (scalar plus scalar): Contiguous load signed halfwords to vector (scalar index)

LD1SH { Zt.S }, Pg/Z, [Xn, Xm, LSL #1] (SVE (SME
svint32_t svld1sh_s32(svbool_t pg, const int16_t *base)
svuint32_t svld1sh_u32(svbool_t pg, const int16_t *base)

128-bit SVE

Load 16-bit values from the memory operand (1) and sign extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

256-bit SVE

Load 16-bit values from the memory operand (1) and sign extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

512-bit SVE

Load 16-bit values from the memory operand (1) and sign extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

Larger sizes

1024-bit SVE

Load 16-bit values from the memory operand (1) and sign extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

2048-bit SVE

Load 16-bit values from the memory operand (1) and sign extend them, writing the results to the 32-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.