SVE Instruction List by Dougall Johnson
LD1SH (scalar plus vector): Gather load signed halfwords to vector (vector index)
LD1SH { Zt.D }, Pg/Z, [Xn, Zm.D, SXTW #1] (SVE+NS
LD1SH { Zt.D }, Pg/Z, [Xn, Zm.D, UXTW #1] (SVE+NS
128-bit SVE
Gather (load) and sign extend 16-bit values into the 64-bit elements of (3), from a base address (Xn/base), plus each corresponding sign-or-zero-extended 32-bit offset from the low halves of the 64-bit elements of (2) multiplied by two. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
256-bit SVE
Gather (load) and sign extend 16-bit values into the 64-bit elements of (3), from a base address (Xn/base), plus each corresponding sign-or-zero-extended 32-bit offset from the low halves of the 64-bit elements of (2) multiplied by two. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
512-bit SVE
Gather (load) and sign extend 16-bit values into the 64-bit elements of (3), from a base address (Xn/base), plus each corresponding sign-or-zero-extended 32-bit offset from the low halves of the 64-bit elements of (2) multiplied by two. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
Larger sizes
1024-bit SVE
Gather (load) and sign extend 16-bit values into the 64-bit elements of (3), from a base address (Xn/base), plus each corresponding sign-or-zero-extended 32-bit offset from the low halves of the 64-bit elements of (2) multiplied by two. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
2048-bit SVE
Gather (load) and sign extend 16-bit values into the 64-bit elements of (3), from a base address (Xn/base), plus each corresponding sign-or-zero-extended 32-bit offset from the low halves of the 64-bit elements of (2) multiplied by two. If the predicate bit from (1) corresponding to an element in (3) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.