LD1W (scalar plus immediate, consecutive registers): Contiguous load of words to multiple consecutive vectors (immediate index)

LD1W { Zt1.S, Zt2.S, Zt3.S, Zt4.S }, PNg/Z, [Xn{, #imm, MUL VL}] (SVE2.1 (SME2+S

Load 32-bit values from the memory operand (1) into the 32-bit elements of four consecutive registers (2), (3), (4), and (5). After decoding the predicate from its predicate-as-counter representation to a quadruple-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by four.

Load 32-bit values from the memory operand (1) into the 32-bit elements of four consecutive registers (2), (3), (4), and (5). After decoding the predicate from its predicate-as-counter representation to a quadruple-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by four.

Load 32-bit values from the memory operand (1) into the 32-bit elements of four consecutive registers (2), (3), (4), and (5). After decoding the predicate from its predicate-as-counter representation to a quadruple-length predicate, if the predicate bit corresponding to an element is zero, that load is skipped, and cannot cause a fault, and the element is set to zero. The first destination register number (2) must be divisible by four.