SVE Instruction List by Dougall Johnson
LD1W (scalar plus immediate, single register): Contiguous load unsigned words to vector (immediate index)
LD1W { Zt.Q }, Pg/Z, [Xn{, #imm, MUL VL}] (SVE2.1+NS
128-bit SVE
Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
256-bit SVE
Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
512-bit SVE
Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
Larger sizes
1024-bit SVE
Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
2048-bit SVE
Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 128-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.