SVE Instruction List by Dougall Johnson
See "LD1W (scalar plus immediate, single register)" in the exploration tools

LD1W (scalar plus immediate, single register): Contiguous load unsigned words to vector (immediate index)

LD1W { Zt.D }, Pg/Z, [Xn{, #imm, MUL VL}] (SVE (SME
svint64_t svld1uw_vnum_s64(svbool_t pg, const uint32_t *base, int64_t vnum)
svuint64_t svld1uw_vnum_u64(svbool_t pg, const uint32_t *base, int64_t vnum)

128-bit SVE

Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

256-bit SVE

Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

512-bit SVE

Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

Larger sizes

1024-bit SVE

Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

2048-bit SVE

Load 32-bit values from the memory operand (1) and zero extend them, writing the results to the 64-bit elements of (2). If the predicate bit corresponding to an element in (2) is zero, that load is skipped, and cannot cause a fault, and the element is set to zero.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.