SVE Instruction List by Dougall Johnson
LD2D (scalar plus immediate): Contiguous load two-doubleword structures to two vectors (immediate index)
LD2D { Zt1.D, Zt2.D }, Pg/Z, [Xn{, #imm, MUL VL}] (SVE (SME
svfloat64x2_t svld2_vnum[_f64](svbool_t pg, const float64_t *base, int64_t vnum)
svint64x2_t svld2_vnum[_s64](svbool_t pg, const int64_t *base, int64_t vnum)
svuint64x2_t svld2_vnum[_u64](svbool_t pg, const uint64_t *base, int64_t vnum)
128-bit SVE
Load and deinterleave pairs of interleaved 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
256-bit SVE
Load and deinterleave pairs of interleaved 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
512-bit SVE
Load and deinterleave pairs of interleaved 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
Larger sizes
1024-bit SVE
Load and deinterleave pairs of interleaved 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
2048-bit SVE
Load and deinterleave pairs of interleaved 64-bit values from the memory operand (1) into the 64-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.