SVE Instruction List by Dougall Johnson
LD2H (scalar plus immediate): Contiguous load two-halfword structures to two vectors (immediate index)
LD2H { Zt1.H, Zt2.H }, Pg/Z, [Xn{, #imm, MUL VL}] (SVE (SME
svbfloat16x2_t svld2_vnum[_bf16](svbool_t pg, const bfloat16_t *base, int64_t vnum)
svfloat16x2_t svld2_vnum[_f16](svbool_t pg, const float16_t *base, int64_t vnum)
svint16x2_t svld2_vnum[_s16](svbool_t pg, const int16_t *base, int64_t vnum)
svuint16x2_t svld2_vnum[_u16](svbool_t pg, const uint16_t *base, int64_t vnum)
128-bit SVE
Load and deinterleave pairs of interleaved 16-bit values from the memory operand (1) into the 16-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
256-bit SVE
Load and deinterleave pairs of interleaved 16-bit values from the memory operand (1) into the 16-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
512-bit SVE
Load and deinterleave pairs of interleaved 16-bit values from the memory operand (1) into the 16-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
Larger sizes
1024-bit SVE
Load and deinterleave pairs of interleaved 16-bit values from the memory operand (1) into the 16-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
2048-bit SVE
Load and deinterleave pairs of interleaved 16-bit values from the memory operand (1) into the 16-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.