SVE Instruction List by Dougall Johnson
LD2Q (scalar plus scalar): Contiguous load two-quadword structures to two vectors (scalar index)
LD2Q { Zt1.Q, Zt2.Q }, Pg/Z, [Xn, Xm, LSL #4] (SVE2.1 (SME2.1
128-bit SVE
Load and deinterleave pairs of interleaved 128-bit values from the memory operand (1) into the 128-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
256-bit SVE
Load and deinterleave pairs of interleaved 128-bit values from the memory operand (1) into the 128-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
512-bit SVE
Load and deinterleave pairs of interleaved 128-bit values from the memory operand (1) into the 128-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
Larger sizes
1024-bit SVE
Load and deinterleave pairs of interleaved 128-bit values from the memory operand (1) into the 128-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
2048-bit SVE
Load and deinterleave pairs of interleaved 128-bit values from the memory operand (1) into the 128-bit elements of two consecutive registers (2) and (3). If the predicate bit corresponding to an element in (2) and (3) is zero, those two contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.