SVE Instruction List by Dougall Johnson
LD3D (scalar plus scalar): Contiguous load three-doubleword structures to three vectors (scalar index)
LD3D { Zt1.D, Zt2.D, Zt3.D }, Pg/Z, [Xn, Xm, LSL #3] (SVE (SME
svfloat64x3_t svld3[_f64](svbool_t pg, const float64_t *base)
svint64x3_t svld3[_s64](svbool_t pg, const int64_t *base)
svuint64x3_t svld3[_u64](svbool_t pg, const uint64_t *base)
128-bit SVE
Load and deinterleave groups of three interleaved 64-bit values from the memory operand (1) into the 64-bit elements of three consecutive registers (2), (3), and (4). If the predicate bit corresponding to an element in (2), (3), and (4) is zero, those three contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
256-bit SVE
Load and deinterleave groups of three interleaved 64-bit values from the memory operand (1) into the 64-bit elements of three consecutive registers (2), (3), and (4). If the predicate bit corresponding to an element in (2), (3), and (4) is zero, those three contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
512-bit SVE
Load and deinterleave groups of three interleaved 64-bit values from the memory operand (1) into the 64-bit elements of three consecutive registers (2), (3), and (4). If the predicate bit corresponding to an element in (2), (3), and (4) is zero, those three contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
Larger sizes
1024-bit SVE
Load and deinterleave groups of three interleaved 64-bit values from the memory operand (1) into the 64-bit elements of three consecutive registers (2), (3), and (4). If the predicate bit corresponding to an element in (2), (3), and (4) is zero, those three contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
2048-bit SVE
Load and deinterleave groups of three interleaved 64-bit values from the memory operand (1) into the 64-bit elements of three consecutive registers (2), (3), and (4). If the predicate bit corresponding to an element in (2), (3), and (4) is zero, those three contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.