SVE Instruction List by Dougall Johnson
LD4H (scalar plus scalar): Contiguous load four-halfword structures to four vectors (scalar index)
LD4H { Zt1.H, Zt2.H, Zt3.H, Zt4.H }, Pg/Z, [Xn, Xm, LSL #1] (SVE (SME
svbfloat16x4_t svld4[_bf16](svbool_t pg, const bfloat16_t *base)
svfloat16x4_t svld4[_f16](svbool_t pg, const float16_t *base)
svint16x4_t svld4[_s16](svbool_t pg, const int16_t *base)
svuint16x4_t svld4[_u16](svbool_t pg, const uint16_t *base)
128-bit SVE
Load and deinterleave groups of four interleaved 16-bit values from the memory operand (1) into the 16-bit elements of four consecutive registers (2), (3), (4), and (5). If the predicate bit corresponding to an element in (2), (3), (4), and (5) is zero, those four contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
256-bit SVE
Load and deinterleave groups of four interleaved 16-bit values from the memory operand (1) into the 16-bit elements of four consecutive registers (2), (3), (4), and (5). If the predicate bit corresponding to an element in (2), (3), (4), and (5) is zero, those four contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
512-bit SVE
Load and deinterleave groups of four interleaved 16-bit values from the memory operand (1) into the 16-bit elements of four consecutive registers (2), (3), (4), and (5). If the predicate bit corresponding to an element in (2), (3), (4), and (5) is zero, those four contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
Larger sizes
1024-bit SVE
Load and deinterleave groups of four interleaved 16-bit values from the memory operand (1) into the 16-bit elements of four consecutive registers (2), (3), (4), and (5). If the predicate bit corresponding to an element in (2), (3), (4), and (5) is zero, those four contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
2048-bit SVE
Load and deinterleave groups of four interleaved 16-bit values from the memory operand (1) into the 16-bit elements of four consecutive registers (2), (3), (4), and (5). If the predicate bit corresponding to an element in (2), (3), (4), and (5) is zero, those four contiguous loads are skipped, and cannot cause a fault, and the elements are set to zero.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.