SVE Instruction List by Dougall Johnson
LDR (vector): Load vector register
LDR Zt, [Xn{, #imm, MUL VL}] (SVE (SME
128-bit SVE
Load a vector register from memory. On 128-bit SVE, this loads 16 bytes from memory (1), into a 128-bit register (2), with the address is calculated as Xn + imm * 16.
256-bit SVE
Load a vector register from memory. On 256-bit SVE, this loads 32 bytes from memory (1), into a 256-bit register (2), with the address is calculated as Xn + imm * 32.
512-bit SVE
Load a vector register from memory. On 512-bit SVE, this loads 64 bytes from memory (1), into a 512-bit register (2), with the address is calculated as Xn + imm * 64.
Larger sizes
1024-bit SVE
Load a vector register from memory. On 1024-bit SVE, this loads 128 bytes from memory (1), into a 1024-bit register (2), with the address is calculated as Xn + imm * 128.
2048-bit SVE
Load a vector register from memory. On 2048-bit SVE, this loads 256 bytes from memory (1), into a 2048-bit register (2), with the address is calculated as Xn + imm * 256.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.