See "LSR (wide elements, predicated)" in the exploration tools

LSR (wide elements, predicated): Logical shift right by 64-bit wide elements (predicated)

LSR Zdn.B, Pg/M, Zdn.B, Zm.D (SVE (SME

svuint8_t svlsr_wide[_u8]_m(svbool_t pg, svuint8_t op1, svuint64_t op2)

128-bit SVE

For each 8-bit unsigned integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 7 or less than 0, the result is 0.

256-bit SVE

For each 8-bit unsigned integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 7 or less than 0, the result is 0.

512-bit SVE

For each 8-bit unsigned integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 7 or less than 0, the result is 0.

Larger sizes

1024-bit SVE

For each 8-bit unsigned integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 7 or less than 0, the result is 0.

2048-bit SVE

For each 8-bit unsigned integer set (3) to (2) shifted right by the corresponding 64-bit value from (1). If the shift amount from (1) is greater than 7 or less than 0, the result is 0.

Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.