SVE Instruction List by Dougall Johnson
LSR (vectors): Logical shift right by vector (predicated)
LSR Zdn.H, Pg/M, Zdn.H, Zm.H (SVE (SME
svuint16_t svlsr[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
128-bit SVE
For each 16-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 15 or less than 0, the result is 0.
256-bit SVE
For each 16-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 15 or less than 0, the result is 0.
512-bit SVE
For each 16-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 15 or less than 0, the result is 0.
Larger sizes
1024-bit SVE
For each 16-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 15 or less than 0, the result is 0.
2048-bit SVE
For each 16-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 15 or less than 0, the result is 0.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.